Growth of unfaceted sige along a semiconductor device width

ABSTRACT

Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable sidewall structures, are formed on sidewalls of the disposable gates. An epitaxially grown silicon germanium is formed in recesses defined by the sidewalls. The process provides a compressive strained channel in the device without faceting of the epitaxially grown silicon germanium.

RELATED APPLICATION

This application claims priority to Ser. No. 61/016,925 filed Dec. 27, 2007, which is entitled “Growth of Unfaceted Sige Along a Semiconductor Device Width.”

FIELD OF INVENTION

The present invention relates generally to semiconductor devices and associated methods of manufacture.

BACKGROUND OF THE INVENTION

A conventional MOS transistor generally includes a semiconductor substrate, such as silicon, having a source, a drain, and a channel positioned between the source and drain. A gate stack composed of a conductive material (a gate conductor), an oxide layer (a gate oxide), and sidewall spacers, is typically located above the channel. The gate oxide is typically located directly above the channel, while the gate conductor, generally comprised of polycrystalline silicon (polysilicon) material, is located above the gate oxide. The sidewall spacers protect the sidewalls of the gate conductor.

Generally, for a given electric field across the channel of a MOS transistor, the amount of current that flows through the channel is directly proportional to a mobility of carriers in the channel. Thus the higher the mobility of the carriers in the channel, the more current can flow and the faster a circuit can perform when using high mobility MOS transistors. One way to increase the mobility of the carriers in the channel of an MOS transistor is to produce a mechanical stress in the channel.

A compressive strained channel has significant hole mobility enhancement over conventional devices. A tensile strained channel, such as a thin silicon channel layer grown on relaxed silicon-germanium, achieves significant electron mobility enhancement. The most common method of introducing tensile strain in a silicon channel region is to epitaxially grow the silicon channel layer on a relaxed silicon-germanium (SiGe), layer or substrate. The ability to form a relaxed SiGe layer is important in obtaining an overlying, epitaxially grown, silicon layer under biaxial tensile strain, however the attainment of the relaxed SiGe layer can be costly and difficult to achieve.

Another prior art method of obtaining a compressive strain in the channel is to epitaxially grow a SiGe layer over the entire active area. However, processes using selective epitaxial deposition for the engineering of elevated source/drain regions often result in overgrowth of the SiGe layer, typically on the order of 300 to 400 Å. Such overgrowth on free surfaces results in faceting of edges due to minimization of interfacial energy causing strain relaxation along corners and potential strain in the channel. Similar to free surfaces, faceting also occurs in the presence of an oxide. Thus, SiGe along the edge of a shallow trench isolation (STI) is faceted, resulting in decreased strain in narrow devices.

It would be advantageous to have a semiconductor device and method that effectively and reliably provides strain to the device without the problems associated with faceting.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.

In one embodiment, the invention is directed to a method of forming a semiconductor device comprising forming gates over a substrate, the gates including disposable gates overlying isolation regions; forming sidewall structures on sidewalls of the gates, including disposable sidewall structures on sidewalls of disposable gates; forming recesses in areas defined by sidewall structures; and filling with an epitaxially grown semiconductor material; forming a source region and a drain region by doping a first portion and a second portion of active regions adjacent a gate; activating the dopants in the source region and the drain region by heating the active regions.

In another embodiment, the invention is directed to a semiconductor device comprising a gate structure over a substrate; a source and a drain adjacent the gate structure; one or more disposable structures formed over a shallow trench isolation region; a semiconductor material comprising an epitaxially grown silicon germanium material in the source and in the drain wherein epitaxial growth occurs in areas defined by disposable structures; and a silicide contact contacting a portion of the source and drain regions.

In a further embodiment, the invention is directed to a semiconductor device comprising a gate structure, including a disposable gate over isolation regions; sidewall structures on sidewalls of the gates, including disposable sidewall structures on sidewalls of disposable gates; recesses in areas defined by sidewall structures; and an epitaxially grown semiconductor material filling the recesses.

The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart illustrating a method of forming a semiconductor device according to one aspect of the invention; and

FIGS. 2A-2I and 2K-2I are fragmentary cross section diagrams illustrating various steps of forming NMOS and PMOS transistors in accordance with the invention of FIG. 1.

FIG. 2J is a top plan view of a semiconductor device on the middle of a source/drain region in accordance with the invention.

FIG. 3 is a flow chart illustrating a method of forming a semiconductor device according to an alternative aspect of the invention.

FIG. 4 is a fragmentary cross section diagram illustrating a step of forming NMOS and PMOS transistors in accordance with the method of FIG. 3.

FIG. 5 is a cross section along the width of a source/drain region in accordance with an embodiment of the invention.

FIG. 6 is a top plan view of a semiconductor device on the middle of a source/drain region.

FIGS. 7A-7B are cross sections along the width of the source/drain region of FIG. 6 illustrating a narrow width and a wide width device formed in accordance with conventional methods.

DETAILED DESCRIPTION OF THE INVENTION

One or more implementations of the invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale.

In the following description, reference is made to the accompanying drawings that form a part thereof, and in which are shown, by way of illustration, specific exemplary embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the invention. The following description is, therefore, not to be taken in a limited sense.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to encompass any and all sub-ranges subsumed therein. For example, a range of “less than 10” can include any and all sub-ranges between (and including) the minimum value of zero and the maximum value of 10, that is, and all sub-ranges having a minimum value of equal to or greater than zero and a maximum value of equal to or less than 10, e.g., 1 to 5.

Methods for fabricating semiconductor devices having strain engineering while minimizing defects associated with strained silicon devices, for example, faceting, in accordance with various embodiments of the invention will now be described. Referring now to FIGS. 1 and 2A-2L, further aspects of the invention relating to methods of fabricating semiconductor devices in accordance with the invention are illustrated. In addition, the methods according to the invention embodiments can be implemented in association with the fabrication of IC's and composite transistors illustrated herein, as well as in association with other transistors and structures not illustrated, including but not limited to NMOS and/or PMOS composite transistors.

FIG. 1 illustrates an exemplary method 100 in accordance with the invention, and FIGS. 2A-2L illustrates the exemplary semiconductor device at various stages of fabrication in accordance with the invention. While the exemplary method 100 is illustrated and described below as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the fabrication of ICs and composite transistors illustrated and described herein, as well as in association with other transistors and structures not illustrated, including but not limited to NMOS and/or PMOS composite transistors.

The method 100 begins at 102, wherein device fabrication is initiated and well formation and isolation processing is performed at 104. Act 104 thus defines NMOS and PMOS regions, wherein NMOS regions comprise a P-well in which n-type source/drain regions will later be formed, and PMOS regions comprise an N-well in which p-type source/drain regions will later be formed, respectively. In addition, isolation regions may comprise shallow trench isolation (STI) or field oxide regions (FOX) that serve to define various active areas and electrically isolate various active areas laterally from one another.

The method 100 continues at 106, wherein a gate oxide layer is formed in active areas defined by the various formed isolation regions. In one example, the gate oxide comprises a thin, thermally grown silicon dioxide layer; however, other type gate dielectrics (such as high-k dielectrics) may be formed and are contemplated by the invention. A conductive gate layer is then deposited over the gate oxide at 108 and patterned to form a conductive gate electrode. For example, a polysilicon layer may be deposited via chemical vapor deposition (CVD) and patterned via etching to form gate electrodes in both NMOS and PMOS regions, respectively, as well as disposable or “dummy” gates over isolation regions.

An offset spacer is then formed on lateral edges of the conductive gate electrodes and dummy gate electrodes at 110. For example, a thin offset layer (e.g., an oxide or nitride layer) is formed generally conformally over the patterned gate and then etched using a generally anisotropic dry etch to remove offset layer material on top of the gate and in the source/drain regions, leaving a thin offset spacer material on lateral edges of the gate. The offset spacer, as will be further appreciated below, is employed in this example to space away the strain inducing material slightly away from the channel region under the gate, for example, a distance of about 5 nm to about 30 nm.

Extension region implants can then be formed at 112 where p-type dopants are implanted in the PMOS region to form a p-type extension region, and n-type dopants are implanted in the NMOS region to form an n-type extension region.

Still referring to FIG. 1, sidewall spacers are then formed on the gate structures at 114, including disposable or “dummy” sidewall spacers on the dummy gate electrodes. The sidewall spacers comprise an insulating material such as an oxide, a nitride or a combination of such layers. The spacers are formed by depositing a layer of such spacer material(s) over the device in a generally conformal manner, followed by an anisotropic etch thereof, thereby removing such spacer material from the top of the gate structure and from the moat or active area and leaving a region on the lateral edges of the gate structure, overlying the offset spacers. The sidewall spacers are substantially thicker than the offset spacers, thereby resulting in the subsequently formed source/drain regions to be offset from lateral edges of the gate structure at least about 60 nm.

A recess is then formed in the moat area extending between the gate structure and the isolation regions at 116 in the PMOS region. The moat area refers to the active region of the silicon body where extension regions and subsequently source/drain regions may be formed. The recess is formed using, for example, a dry etching process such as the chemistry employed to etch STI trenches in the semiconductor body when forming isolation regions. Gate structure can be masked (not shown) so as to prevent formation of a recess in the top portion of the gate.

At 118, sidewall spacers may be removed. Where sidewall spacers were formed from an oxide, spaces are removed by known etching techniques. Spacers formed from a nitride insulating material may be left in place.

The method 100 then continues at 120, wherein silicon germanium is formed in the recesses in the PMOS region. In one example, the silicon germanium is formed via a selective epitaxial deposition process such as an LPCVD (low pressure chemical vapor deposition) process using dichlorosilane and germane as the source gases. While not intending to be limited to any one theory, it is believed that the silicon germanium within the recesses form an alloy that has a lattice with the same structure as the silicon body lattice, however, the silicon germanium has a larger spacing. Consequently, it is believed that the silicon germanium within the recesses will tend to expand, thereby creating a compressive stress within the channel of the semiconductor body underneath the channel.

After filling recesses with semiconductor material (e.g., silicon germanium) source/drain sidewall spacers can be formed at 122. Source/drain sidewall spacers comprise an insulating material such as an oxide, a nitride, or a combination of such layers. Sidewall spacers can be formed as described hereinabove. The source/drain regions are then formed by implantation at 124, wherein a source/drain dopant is introduced into the exposed areas (top of gate electrode and active areas not covered by sidewall spacers). The source/drain regions are then completed with a thermal process to activate the dopant.

The method 100 then concludes with silicide processing at 126, wherein a metal layer is formed over the device, followed by a thermal process, wherein the metal and silicon interfaces react to form a silicide (on top of the gate and in the source/drain regions). Unreacted metal is then stripped away, and back end processing such as interlayer dielectric and metallization layers are formed at 128 to conclude the device formation at 130.

Turning now to FIGS. 2A-2K, a plurality of fragmentary cross section diagrams illustrating a transistor device being formed in accordance with the method of FIG. 1 is provided. In FIG. 2A, a transistor device 202 is provided, wherein a semiconductor body 204, such as a substrate, has a number of wells formed therein, such as a P-well 206 to define an NMOS transistor device region and an N-well 208 to define a PMOS transistor device region, respectively. Further, isolation regions 210 such as field oxide (FOX) or STI regions are formed in the semiconductor body to define active area regions 211.

In FIG. 2B, the transistor device 202 is illustrated, wherein a gate dielectric 212 has been formed, for example, thermally grown SiO₂, over the active areas 211. However, other types of gate dielectrics (such as high-k dielectrics) can be formed and are contemplated by the various embodiments.

Referring to FIGS. 2C and 2D, a conductive gate electrode material, such as, for example, polysilicon, can be deposited and patterned by an etching process 215 to form a gate electrode 214 overlying the gate oxide 212. Concurrently, dummy gates 213 are formed overlying gate oxide 212 in STI regions 210. Offset spacer 216 can then be formed on the lateral edges of the gate electrode 214 and dummy gate electrode 213, as seen in FIG. 2D, wherein the offset spacers can have a width 216 a of about 10-50 nm.

The PMOS region can then be masked off, as illustrated in FIG. 2E with a masking material 226 such as photoresist, and an extension region implant 228 can be performed to form n-type extension region 230 in the NMOS region. According to various embodiments, a thermal process, such as a rapid thermal anneal, can then be performed to activate the dopant, wherein lateral diffusion of the extension regions 230 under the offset spacer 216 is achieved. Exemplary temperatures for activating dopants are from about 650° C. to about 1050° C. In certain embodiments, the temperature can be about 950° C. and in still further embodiments, the temperature can be about 1050° C. At these temperatures, there is amorphous layer re-growth.

The p-type extension region mask 226 can then be removed, and an n-type extension region mask 232 can be deposited and patterned to cover the NMOS region, as illustrated in FIG. 2F. A p-type extension region implant process 234 can then be performed to form p-type extension regions 236 in the PMOS region, as illustrated.

The mask 232 can then be removed and sidewall spacers 238 can then be formed adjacent offset spacers 216 on the lateral edges of the gate structures 214, including dummy sidewall spacers on dummy gate 213. For example, an insulating sidewall material can be deposited in a generally conformal manner over the device and subsequently subjected to an anisotropic etch to remove the insulating material on top of the gate and over the active areas, leaving sidewall spacers 238 in both the NMOS and PMOS regions, as illustrated in FIG. 2G. Exemplary materials used for the dummy sidewall spacers 238 include various nitrides, such as silicon nitrides. However, other acceptable material can also be used. Dummy sidewall spacers have a width of about 10 nm to about 60 nm.

Recesses 260 can then be formed in the PMOS region in areas defined by sidewall spacers 238 and extending between the gate structure and the isolation regions, as shown in FIG. 2H, while NMOS region is masked (not shown). The area where the recesses are formed can include the active regions of the silicon body where extension regions 230 and 236 and source and drain regions 268 and 270 (FIG. 2K) are formed. Recesses 260 can be formed using, for example, a dry etching technique such as the chemistry employed to etch the STI trenches in the semiconductor body when forming isolation regions. According to an embodiment, the recesses can extend into the semiconductor body to a depth of about 120 nm to about 130 nm. In certain embodiments, the gate structure is not masked during recess formation.

As shown in FIG. 2I, recesses 260 can then be filled with a semiconductor material 265 by a selective epitaxial deposition process 267 whereby a germanium containing gas source such as germane is added to a silane or dichlorosilane, such that a silicon germanium material 265 is formed in the recesses 260. The amount of germanium in the silicon germanium material will be from about 20 at % wt to about 40 at % wt.

Turning to FIG. 6, there is illustrated a top plan view of a source 614/drain 616 having a gate electrode 612 and isolation regions 610, in which FIGS. 7A and 7B illustrate narrow width 613 and large width 617 devices along cutline 618 (FIG. 6), respectively. In conventional methods of forming silicon-germanium layers, epitaxial silicon-germanium growth 612 from recesses, having depth 611, between isolation regions 610 resulted in faceting 615 of the silicon germanium. As illustrated in FIG. 2J, which is a top plan view on the middle of a source/drain, and FIG. 5, which is a cross section along the width 540 of the source/drain region, addition of the dummy gate 213 and dummy sidewall spacers 238 of the invention results in spacing 264 of the recesses 260, having a depth 542, from the STI structures 210, thus allowing for growth of the silicon germanium material 265 vertically 544 along the dummy sidewalls 238 and preventing faceting of the silicon germanium along the STI interface. Alternatively, where the STI is an oxide structure, the silicon germanium material 265 will grow from deep within the structure such that near the surface of the STI, the material will be at a lower height. In such a case, the sidewall spacers 238 provide support for the growing silicon germanium front as it grows above the silicon surface, and spacing of the recesses from the STI structures 513 is not necessary.

As shown in FIG. 2K, after filling the recesses with semiconductor material 265, sidewall spacers 238 can be removed and additional sidewall spacers 266 can be formed thereafter. Source and drain regions 268 and 270 can then be formed in the NMOS and PMOS regions respectively, as shown in FIG. 2K. As discussed above in conjunction with the extension region implants, the source/drain implants can be performed with a n-source/drain mask (not shown) and a p-source/drain mask (not shown) in order to implant the NMOS region and the PMOS region separately with n-type and p-type dopant, respectively.

According to various embodiments, as shown for example in FIG. 2L which is an enlarged view of a resulting PMOS transistor fabricated in accordance with the invention, a silicide 280 can then be formed. For example, a metal layer can be deposited, for example, by sputtering, followed by a thermal process. During the thermal process, those regions where the metal contacts silicon reacts to form a metal silicide. More particularly, the silicide can then form on the source/drain regions and on top of the gates. Unreacted metal is then stripped away, and back end processing such as interlayer dielectric and metallization layers are formed so as to conclude the device formation.

In an alternative embodiment of the invention, and referring to FIGS. 3 and 4, there is illustrate a method 300 in accordance with the invention, in which semiconductor processing proceeds as in method 200. However, sidewall spacers 338 (FIG. 4) remain and a second set of sidewall spacers 366 are formed following the filling of recesses with semiconductor material, as illustrated in FIG. 4.

In addition, while the invention is described above with respect to the use of germanium to form a silicon germanium lattice structure, the present invention contemplates the use of any element that will create an alloy with silicon and serve to impart a compressive stress to the channel of the PMOS devices, and such alternatives are contemplated as falling within the scope of the invention.

While the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”. 

1. A method of forming a semiconductor device comprising: forming gates over a substrate, the gates including disposable gates overlying isolation regions; forming sidewall structures on sidewalls of the gates, including disposable sidewall structures on sidewalls of disposable gates; forming recesses in areas defined by sidewall structures; and filling with an epitaxially grown semiconductor material; forming a source region and a drain region by doping a first portion and a second portion of an active regions adjacent a gate; activating the dopants in the source region and the drain region by heating the active regions.
 2. The method of claim 1, wherein the substrate is a silicon substrate.
 3. The method of claim 1, wherein recesses extend into substrate to a depth of about 120 nm to about 130 nm.
 4. The method of claim 3, wherein the disposable sidewall spacers have a width of about 10 nm to about 60 nm.
 5. The method of claim 3, wherein the disposable sidewall spacer comprises a silicon nitride.
 6. The method of claim 1, wherein the semiconductor material comprises silicon germanium.
 7. The method of claim 3, wherein the amount of germanium present in the semiconductor material is from about 20 at wt % to about 40 at wt %.
 8. The method of claim 1, wherein the semiconductor material deposited forms a strained region with respect to the surrounding source region and drain region, respectively.
 9. The method of claim 1, further comprising removing disposable gate and sidewall structures from the isolation region.
 10. A semiconductor device comprising: a gate structure, including a disposable gate over isolation regions; sidewall structures on sidewalls of the gates, including disposable sidewall structures on sidewalls of disposable gates; recesses in areas defined by sidewall structures; and an epitaxially grown semiconductor material filling the recesses.
 11. The semiconductor device of claim 10, wherein recesses extend into substrate to a depth of about 120 nm to about 130 nm.
 12. The semiconductor device of claim 11 wherein the disposable sidewall spacers have a width of about 10 nm to about 60 nm.
 13. The semiconductor device of claim 11, wherein the disposable sidewall spacer comprises a silicon nitride.
 14. The semiconductor device of claim 10, wherein the semiconductor material comprises silicon germanium.
 15. The semiconductor device of claim 12, wherein the amount of germanium present in the semiconductor material is from about 20 at wt % to about 40 at wt %.
 16. A semiconductor device comprising: a gate structure over a substrate; a source and a drain adjacent the gate structure; one or more disposable structures formed over a shallow trench isolation region; a semiconductor material comprising an epitaxially grown silicon germanium material in the source and in the drain wherein epitaxial growth occurs in areas defined by disposable structures; and a silicide contact contacting a portion of the source and drain regions.
 17. The semiconductor device of claim 16, wherein the disposable structures comprise a disposable gate and disposable sidewall structures.
 18. The semiconductor device of claim 17, wherein the disposable sidewall spacer comprises a silicon nitride. 